1. Field of the Invention
The present invention relates to a technology for reducing the power consumption in a content addressable memory device.
2. Description of the Related Art
FIG. 17 shows one example of a content addressable memory (hereinafter, referred to as a CAM) device. In the figure, a CAM device 118 includes a CAM cell array 120 having an N bit widthxc3x97M word construction, a decoder 122, a bit line control circuit 124, a match detecting circuit 126, a flag generator 128, and a priority encoder 130. Although not shown, the bit line control circuit 124 includes a bit line precharge circuit, a bit line driver, a sense amplifier, a search data register, a mask register, and the like.
In the CAM device 118, storage data is read and written in the same manner as in a normal RAM. That is, when data is written, the decoder 122 selects a word WL corresponding to an address ADR. The bit line driver drives data DATA as storage data on a bit line BIT and negated data /DATA (the negated signal of data DATA) as storage data on a bit bar line /BIT. The driven data is written in the word WL corresponding to the address ADR.
When data is read, the decoder 122 selects the word WL corresponding to the address ADR. This allows DATA (the storage data) to be read on the bit line and the /DATA to be read on the bit bar line. Thereafter, the sense amplifier detects the read data, and the storage data stored in the word WL corresponding to the address ADR is read as DATA.
Match searching of search data is performed on storage data as follows. After storage data is written to each word of the CAM cell array 120 in the above-described manner, the search data is input as DATA, instructing the start of search. By loading the search data in the search data register, and then driving the search data DATA on the bit line BIT and its negated signal /DATA on the bit bar line /BIT, match searching of the search data is performed on the storage data of every word.
The match detecting circuit 126 corresponding to each word via a match line ML detects a search result. The detected data is input to the flag generator 128 and the priority encoder 130. The flag generator 128 outputs, as a flag, one state of xe2x80x9cno matchingxe2x80x9d, xe2x80x9csingle matchingxe2x80x9d, and xe2x80x9cmultiple matchingxe2x80x9d in accordance with the result. When matching occurs, the priority encoder 130 outputs the memory address of the matched word having a predetermined high priority as a high priority hit address (HHA).
Match searching of the CAM device 118 is described in more detail by giving examples of the CAM cell shown in FIGS. 18A to 18C. The CAM cells shown in these figures are constructed using a SRAM (static random access memory).
In a CAM cell 132 shown in FIG. 18A, match searching is performed by setting the bit line BIT and the bit bar line /BIT to LOW, turning off an N-type MOS (Metal Oxide Semiconductor) transistor 138 (hereinafter, referred to as an NMOS) which is connected between the match line ML and the ground, precharging the potential of the match line ML to the potential of a power source, and driving the search data DATA on the bit line BIT and the search data bar /DATA on the bit bar line /BIT.
When the storage data and the search data match, the gate of the NMOS 138 is maintained at LOW via either an NMOS 134 or an NMOS 136 which is turned on in accordance with the storage data. Therefore, the match line ML remains precharged. However, when the storage data and the search data do not match, a HIGH level signal is input into the gate of the NMOS 138 via either the NMOS 134 or the NMOS 136 which is turned on. Since this turns on the NMOS 138, the match line ML is discharged.
In a CAM cell 140 shown in FIG. 18B, match searching is performed by setting the bit line BIT and the bit bar line /BIT to LOW, turning off an NMOS 146 and an NMOS 148, which are connected to the ground, precharging the potential of the match line ML to the potential of the power source, and then driving the search data DATA on the bit line BIT and the search data bar /DATA on the bit bar line /BIT.
When the storage data and the search data match, either an NMOS 142 or the NMOS 146 is turned off and either an NMOS 144 or the NMOS 148 is turned off in which a pair of the NMOSs 142 and 146 and a pair of the NMOSs 144 and 148 are individually connected in series between the match line ML and the ground. Accordingly, the match line ML remains precharged. When the storage data and the search data do not match, both the NMOS 142 and the NMOS 146 or both the NMOS 144 and the NMOS 148 are turned on. This allows the match line ML to be discharged via the NMOS transistors, both of which are turned on.
In a CAM cell 150 shown in FIG. 18C, match searching is performed by setting the bit line BIT and the bit bar line /BIT to HIGH, turning off two P-type MOS transistors (hereinafter, referred to as a PMOS) 156 and 158, which are connected to the match line ML, discharging the match line ML to the ground potential, and then driving the search data DATA on the bit line BIT and the search data bar /DATA on the bit bar line /BIT.
When the storage data and the search data match, either a PMOS 152 or the PMOS 156 is turned off and either a PMOS 154 or the PMOS 158 is turned off in which a pair of the PMOSs 152 and 156 and a pair of the PMOSs 154 and 158 are individually connected in series between the match line ML and the power source. Accordingly, the match line ML remains discharged. On the other hand, when the storage data and the search data do not match, both the PMOS 152 and the PMOS 156 or both PMOS 154 and the PMOS 158 are turned on. This allows the match line ML to be charged via the PMOS transistors both of which are turned on.
In the case of the CAM device 118 shown in FIG. 17, one word is constructed using N CAM cells, the CAM cells which constitute the same word are connected to the match line ML. Accordingly, the match line ML is maintained at a standby level only when matching is detected on all of the CAM cells constituting the one word. When mismatching is detected in any of the CAM cells constituting the one word, the match line ML is discharged from the standby potential.
The CAM cells 132, 140, and 150 shown in FIGS. 18A to 18C are mismatch-detecting types. When mismatching occurs, the match line ML is discharged/charged so that the logical level of the match line ML becomes the opposite logical level of the precharge potential. However, since storage data of most words are mismatched, when the mismatch-detecting type CAM cells shown in FIGS. 18A to 18C are used, the potentials of most match lines ML are discharged/charged to the opposite logical level of the precharge potential. This means that the potentials of most match lines ML swing from the power source potential to the ground potential every searching cycle.
In the case of each of the CAM cells 132 and 140 in FIGS. 18A and 18B, respectively, the following steps must be executed in order to perform match searching. After normal storage data is read or written, a bit line pair of the bit line BIT and the bit bar line /BIT is precharged to the power source potential during the standby time. During match searching, the bit line pair is discharged to the ground potential and then the match line ML is precharged to the power source potential. Thereafter, either the bit line BIT or the bit bar line /BIT is driven to the power source potential again in accordance with the search data.
That is, in order to precharge the potential of the match line ML, the bit line pair of BIT and /BIT must be temporarily discharged to the ground potential. The amount of current required for these precharging and discharging is dissipated. On the other hand, in the case of the CAM cell 150 in FIG. 18C, the match line ML is discharged, and then either BIT or /BIT of the bit line pair which is precharged to the power source potential is discharged to the ground potential.
Thus, since most match lines ML and the bit line pairs of BITs and /BITs are simultaneously precharged/discharged during searching, the increase in power consumption becomes a problem as the capacity of the CAM device and the processing speed increase. However, in principle, the CAM device must simultaneously compare the search data with all of the storage data. Therefore, unlike the normal RAM, reduction in power consumption cannot be achieved by performing block division, bank division, or the like in the memory arrays so that searching is performed only on the selected block or the selected bank.
Accordingly, it is an object of the present invention to provide a low-power CAM device having higher capacity and faster processing speed by solving the foregoing problems.
To this end, according to a first aspect of the present invention, there is provided a consumption content addressable memory device including a storage bit line pair for reading storage data from and writing storage data to a content addressable memory cell, a search bit line pair, wired independently from the storage bit line pair, for providing search data to the content addressable memory cell, and a first unit for realizing a smaller swing in the level of the search bit line pair by setting the potential of the search bit line pair to an intermediate potential between a power source potential and a ground potential during match searching.
According to a second aspect of the present invention, a content addressable memory device includes a storage bit line pair for reading storage data from and writing storage data to a content addressable memory cell, a search bit line pair, wired independently from the storage bit line pair, for providing search data to the content addressable memory cell, and a second unit for realizing a smaller swing in the level of a match line by setting a precharge level of the match line to an intermediate potential between a power source potential and a ground potential, wherein the match line outputs a result of match searching of the storage data for the search data.
According to a third aspect of the present invention, a content addressable memory device includes a storage bit line pair for reading storage data from and writing storage data to a content addressable memory cell, a search bit line pair, wired independently from the storage bit line pair, for providing search data to the content addressable memory cell, a first unit for realizing a smaller swing in the level of the search bit line pair by setting the potential of the search bit line pair to an intermediate potential between a power source potential and a ground potential during match searching, and a second unit for realizing a smaller swing in the level of a match line by setting a precharge level of the match line to an intermediate potential between the power source potential and the ground potential, wherein the match line outputs a result of match searching of the storage data for the search data.
In CAM, among the storage bit line and the search bit line, the search bit line has much more responsibility for power consumption during charging and discharging. This is because only the storage bit lines corresponding to a selected column are activated during storage data reading and writing while all search bit lines to be searched must be activated during searching. In the present invention, the level of the storage bit line may be swung from the ground potential to the power source potential same as in a conventional manner. Alternatively, the level of the storage bit line may be swung based on the intermediate potential in the same manner as the level of the search bit line. However, by causing the storage bit line to be operated between the ground potential and the power source potential, power consumption of CAM can be greatly reduced while the processing speeds and the stabilities of the reading/writing operations are maintained.
Further objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments with reference to the attached drawings.